PCIe access port parameters.
The following model shows SoC's PCIe module connects to multiple PCIe hosts and multiple endpoints. The PCIe module has an integrated DMA controller.
If the DMA wants to access the memory of host A, it can be initiated by PF1 in core0, or by VF0 of PF0 in core0.
System Bus
| ----------PCIe module----------
| Bus
| Interface
| ----- ------------------
| | | | PCIe Core0 |
| | | | | -----------
| | | | PF-0 -- VF-0 | | Host A |
| | |--------| |- VF-1 |--------| Root |
| | | | PF-1 | | Complex |
| | | | PF-2 | -----------
| | | ------------------
| | |
| | | ------------------
| | | | PCIe Core1 |
| | | | | -----------
| | | | PF-0 -- VF-0 | | Host B |
|-----| |--------| PF-1 -- VF-0 |--------| Root |
| | | | |- VF-1 | | Complex |
| | | | PF-2 | -----------
| | | ------------------
| | |
| | | ------------------
| |DMA| | | ------
| | | | |--------| EP |
| | |--------| PCIe Core2 | ------
| | | | | ------
| | | | |--------| EP |
| | | | | ------
| ----- ------------------
- Note
- If some fields can not be supported by the hardware/driver, then the driver ignores those fields. Please check driver-specific documentation for limitations and capabilities.
Definition at line 554 of file rte_dmadev.h.
1.18.0